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Einrichtungen >> Technische Fakultät (TF) >> Department Informatik (INF) >>

Lehrstuhl für Informatik 12 (Hardware-Software-Co-Design)

	2016 A Binary Time Series Model of LTE Scheduling for Machine Learning Prediction A heterogeneous multi-core SoC for mixed criticality industrial automation systems A High-Performance Image Processing DSL for Heterogeneous Architectures A LUT-Based Approximate Adder A New Time-Independent Reliability Importance Measure A Novel Image Impulse Noise Removal Algorithm Optimized for Hardware Accelerators A Novel NoC-Architecture for Fault Tolerance and Power Saving A Quick Tour of High-Level Synthesis Solutions for FPGAs ActorX10: An Actor Library for X10 Analysis and Exploitation of CTU-Level Parallelism in the HEVC Mode Decision Process Using Actor-based Modeling Big Data and HPC Acceleration with Vivado HLS Dark Silicon Management: An Integrated and Coordinated Cross-Layer Approach Exploration of Power Domain Partitioning for Application-Specific SoCs in System-Level Design Fairness in Academic Course Timetabling FAU: Fast and Error-Optimized Approximate Adder Units on LUT-Based FPGAs Formal Reliability Analysis of Switched Ethernet Automotive Networks under Transient Transmission Errors FPGA versus Software Programming: Why, When, and How? FPGA-based Accelerator Design from a Domain-Specific Language FPGA-Based Dynamically Reconfigurable SQL Query Processing FPGAs for Software Programmers Guiding Genetic Algorithms Using Importance Measures for Reliable Design of Embedded Systems Hierarchical Statistical Leakage Analysis and its Application HIPAcc HIPAcc: A Domain-Specific Language and Compiler for Image Processing Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures Hybrid Energy-Aware Reconfiguration Management on Xilinx Zynq SoCs InvadeSIM: A Simulator for Heterogeneous Multi-Processor Systems-on-Chip Invasive Computing - Editorial Invasive Computing for Timing-Predictable Stream Processing on MPSoCs Invasive Tightly Coupled Processor Arrays Language and Compilation of Parallel Programs for **-Predictable MPSoC Execution using Invasive Computing LoopInvader: A Compiler for Tightly Coupled Processor Arrays Modeling, Programming and Performance Analysis of Automotive Environment Map Representations on Embedded GPUs Modulo Scheduling of Symbolically Tiled Loops for Tightly Coupled Processor Arrays Multi-Objective Design Space Exploration for the Optimization of the HEVC Mode Decision Process On the Boolean Extension of the Birnbaum Importance to Non-Coherent Systems Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-Core Processor Position Paper: Towards Redundant Communication through Hybrid Application Mapping Power Density-Aware Resource Management for Heterogeneous Tiled Multicores Proc. of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) Proceedings of the 29th International Conference on Architecture of Computing Systems (ARCS) Providing Fault Tolerance Through Invasive Computing Providing security on demand using invasive computing Recap of the 2016 DATE Conference & Exhibition ReOrder: Runtime Datapath Generation for High-Throughput Multi-Stream Processing Simulating shallow water waves with lazy activation of patches using ActorX10 Supporting Composition in Symbolic System Synthesis Systems of Partial Differential Equations in ExaSlang Timing Verification of Realtime Automotive Networks: What can we expect from Simulation? Vision-Based Path Construction and Maintenance for Indoor Guidance of Autonomous Ground Vehicles Based on Collaborative Smart Cameras
	2015 A Clustering-Based MPSoC Design Flow for Data Flow-Oriented Applications A Co-Design Approach for Accelerated SQL Query Processing via FPGA-based Data Filtering A Co-Design Approach for Fault-Tolerant Loop Execution on Coarse-Grained Reconfigurable Arrays A Methodology for the Optimized Design of an E/E Architecture Component Platform A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms Adaptive Fault Tolerance in Tightly Coupled Processor Arrays with Invasive Computing Adaptive Fault Tolerance through Invasive Computing Adaptive Isolation for Predictable MPSoC Stream Processing Application-aware cross-layer reliability analysis and optimization Approximate Adder Structures on FPGAs Automatic Communication-driven Virtual Prototyping and Design for Networked Embedded Systems Automatic Optimization of Hardware Accelerators for Image Processing Bridging Algorithm and ESL Design: MATLAB/Simulink Model Transformation and Validation Code Generation for Tightly Coupled Processor Arrays Compact Code Generation and Throughput Optimization for Coarse-Grained Reconfigurable Arrays Degree-constrained Subgraph Reconfiguration is in P Design and Optimization of Multi-Variant Automotive E/E Architecture Component Platforms Design Methodology and Run-time Management for Predictable Many-Core Systems Execution-driven Parallel Simulation of PGAS Applications on Heterogeneous Tiled Architectures Explanation of Stagnation at Points that are not Local Optima in Particle Swarm Optimization by Potential Analysis Fairness in Academic Course Timetabling Fault-tolerant Communication in Invasive Networks on Chip Formal Analysis of the Startup Delay of SOME/IP Service Discovery Generation of Multigrid-based Numerical Solvers for FPGA Accelerators Importance Measures in Time-dependent Reliability Analysis and System Design Insights on the Configuration and Performances of SOME/IP Service Discovery Introduction to the Special Issue on Testing, Prototyping, and Debugging of Multi-Core Architectures Invasive Computing for Predictable Stream Processing: A Simulation-based Case Study Invasive Tightly Coupled Processor Arrays Loop Coarsening in C-based High-Level Synthesis Multimodal Medical Image Registration Using Particle Swarm Optimization with Influence of the Data's Initial Orientation Network Interface with Task Spawning Support for NoC-based DSM Architectures On-Demand Fault-Tolerant Loop Processing on Massively Parallel Processor Arrays Particle Swarm Optimization Almost Surely Finds Local Optima Position Paper: Towards Hardware-Assisted Decentralized Mapping of Applications for Heterogeneous NoC Architectures Proceedings of the 2nd International Workshop on FPGAs for Software Programmers (FSP) Proceedings of the DATE Friday Workshop on Heterogeneous Architectures and Design Methods for Embedded Image Systems (HIS 2015) Quasi-Static Scheduling of Data Flow Graphs in the Presence of Limited Channel Capacities Rapid Prototyping for Hardware Accelerators in the Medical Imaging Domain Reconfigurable Buffer Structures for Coarse-Grained Reconfigurable Arrays Reliability of Space-Grade vs. COTS SRAM-Based FPGA in N-Modular Redundancy Resource Awareness on Heterogeneous MPSoCs for Image Processing Robust Design of E/E Architecture Component Platforms Runtime Adaptation of Application Execution under Thermal and Power Constraints in Massively Parallel Processor Arrays Symbolic Loop Parallelization for Balancing I/O and Memory Accesses on Processor Arrays Symbolic Message Routing for Multi-Objective Optimization of Automotive E/E Architecture Component Platforms Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge System-Level Power and Performance Estimation in Early SoC Design Phases Techniques for On-Demand Structural Redundancy for Massively Parallel Processor Arrays Throughput-optimizing Compilation of Dataflow Applications for Multi-Cores using Quasi-Static Scheduling Uncertainty-Aware Reliability Analysis and Optimization
	2014 A Scala Prototype to Generate Multigrid Solver Implementations for Different Problems and Target Multi-Core Platforms A Self-Propagating Wakeup Mechanism for Point-to-Point Networks with Partial Network Support Advanced Diagnosis: SBST and BIST Integration in Automotive E/E Architectures An Efficient Technique for Computing Importance Measures in Automatic Design of Dependable Embedded Systems An Evaluation of Domain-Specific Language Technologies for Code Generation An Image Processing Library for C-based High-Level Synthesis Application-driven Reconfiguration of Shared Resources for Timing Predictability of MPSoC Platforms Automatic Graph-based Success Tree Construction and Analysis CAP: Communication Aware Programming Code Generation for Embedded Heterogeneous Architectures on Android Code Generation for High-Level Synthesis of Multiresolution Applications on FPGAs Code Generation from a Domain-specific Language for C-based HLS of Hardware Accelerators Communication-driven Automatic Virtual Prototyping for Networked Embedded Systems Compact Code Generation for Tightly-Coupled Processor Arrays Connecting Different Worlds - Technology Abstraction for Reliability-Aware Design and Test DAARM: Design-Time Application Analysis and Run-Time Mapping for Predictable Execution in Many-Core Systems Design Space Exploration for Automotive E/E Architecture Component Platforms Domain-Specific Augmentations for High-Level Synthesis DPSK Modulated Wakeup Mechanism for Point-to-Point Networks with Partial Network Support End-to-End Power Estimation for Heterogeneous Cellular LTE SoCs in Early Design Phases Energy-Aware SQL Query Acceleration through FPGA-Based Dynamic Partial Reconfiguration ExaSlang: A Domain-Specific Language for Highly Scalable Multigrid Solvers ExaStencils: Advanced Stencil-Code Engineering Experiments on Optimizing the Performance of Stencil Codes with SPL Conqueror High-Level Synthesis Revised - Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model How Much Forcing is Necessary to Let the Results of Particle Swarms Converge? Invasive Tightly-Coupled Processor Arrays: A Domain-Specific Architecture/Compiler Co-Design Approach MAESTRO - Holistic Actor-oriented Modeling of Non-Functional Properties and Firmware Behavior for MPSoCs Mahler: Sketch-based Model-driven Virtual Prototyping Massively Parallel Processor Architectures for Resource-aware Computing Minimizing Scrubbing Effort through Automatic Netlist Partitioning and Floorplanning Model-Based Actor Multiplexing with Application to Complex Communication Protocols Multi-Objective Distributed Run-time Resource Management for Many-Cores Multi-Objective Local-Search Optimization using Reliability Importance Measuring Multi-Variant-based Design Space Exploration for Automotive Embedded Systems Non-Intrusive Integration of Advanced Diagnosis Features in Automotive E/E-Architectures Parametric Yield Optimization Using Leakage-Yield-Driven Floorplanning Proceedings of the First International Workshop on FPGAs for Software Programmers (FSP 2014) Proceedings of the First Workshop on Resource Awareness and Adaptivity in Multi-Core Computing (Racing 2014) Quality-aware Video Decoding on Thermally-constrained MPSoC Platforms Resilience Articulation Point (RAP): Cross-layer Dependability Modeling for Nanometer System-on-Chip Resilience Runtime Reconfigurable Bus Arbitration for Concurrent Applications on Heterogeneous MPSoC Architectures Self-Adaptive Harris Corner Detection on Heterogeneous Many-core Processor Self-Integration for Virtualization of Embedded Many-Core Systems Symbolic Inner Loop Parallelisation for Massively Parallel Processor Arrays Symbolic Mapping of Loop Programs onto Processor Arrays Temperature modeling and emulation of an ASIC temperature monitor system for Tightly-Coupled Processor Arrays (TCPAs) on FPGA The Connectedness of Clash-free Timetables The Invasive Network on Chip - A Multi-Objective Many-Core Communication Infrastructure Timing Analysis of a Heterogeneous Architecture with Massively Parallel Processor Arrays Towards a Better Understanding of the Local Attractor in Particle Swarm Optimization: Speed and Solution Quality Towards a Performance-portable Description of Geometric Multigrid Algorithms using a Domain-specific Language Towards Actor-oriented Programming on PGAS-based Multicore Architectures Towards Scalable Symbolic Routing for Multi-Objective Networked Embedded System Design and Optimization White Paper: Programming Abstractions for Data Locality
	2013 A Combined Mapping and Routing Algorithm for 3D NoCs Based on ASP A Decomposition of the Max-min Fair Curriculum-based Course Timetabling Problem: The Impact of Solving Subproblems to Optimality A Prototype of an Adaptive Computer Vision Algorithm on MPSoC Architecture A Rule-Based Quasi-Static Scheduling Approach for Static Islands in Dynamic Dataflow Graphs Acceleration of Optical Flow Computations on Tightly-Coupled Processor Arrays Acceleration of SQL Restrictions and Aggregations through FPGA-based Dynamic Partial Reconfiguration Accuracy and Performance Analysis of Harris Corner Computation on Tightly-Coupled Processor Arrays AUTO-GS: Self-optimization of NoC Traffic Through Hardware Managed Virtual Connections Automatic Success Tree-Based Reliability Analysis for the Consideration of Transient and Permanent Faults Bridging Algorithm and ESL Design: Matlab/Simulink Model Transformation and Validation Code Generation for GPU Accelerators from a Domain-Specific Language for Medical Imaging Cross-Layer Dependability Modeling and Abstraction in System on Chip Decomposing Run-time Resource Management in Heterogeneous Reconfigurable Systems Design and Evaluation of Future Ethernet AVB-based ECU Networks ESL Power Estimation: A Design Case Study for Early Design Phases Experimental Analysis of Bound Handling Techniques in Particle Swarm Optimization Exploitation of Quality/Throughput Tradeoffs in Image Processing through Invasive Computing Exploiting Independent Subformulas: A Faster Approximation Scheme for #k-SAT Exploration of Distributed Automotive Systems using Compositional Timing Analysis Game-Theoretic Analysis of Decentralized Core Allocation Schemes on Many-core Systems Hardware Supported Adaptive Data Collection for Networks on Chip High-Level Synthesis Revised: Generation of FPGA Accelerators from a Domain-Specific Language using the Polyhedron Model HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN) Integrated Modeling Using Finite State Machines and Dataflow Graphs Invasive Computing - Common Terms and Granularity of Invasion Investigating the Impact of Energy-Efficient Ethernet on Automotive Applications via High-level Modeling IVaM: Implicit Variant Modeling and Management for Automotive Embedded Systems Keynote Talk, Resource-Aware Computing on Domain-Specific Accelerators Loop Program Mapping and Compact Code Generation for Programmable Hardware Accelerators Migration Strategies for Ethernet-based E/E Architectures Model-Based Representation of Schedules for Dataflow Graphs Multi-Platform Performance Evaluation of Pedestrian Detection at the Electronic System Level NoC Simulation in Heterogeneous Architectures for PGAS Programming Model On Confident Task-Accurate Performance Estimation On Robust Task-Accurate Performance Estimation Particle Swarm Optimization Almost Surely Finds Local Optima Particles Prefer Walking Along the Axes: Experimental Insights into the Behavior of a Particle Swarm Real-Time Range Image Preprocessing on FPGAs Representing Mapping and Scheduling Decisions within Dataflow Graphs Run-Time Adaptation for Highly-Complex Multi-Core Systems Scenario-Based Energy Estimation of Heterogeneous Integrated Systems at System Level Self-organizing Core Allocation Symbolic Parallelization of Loop Programs for Massively Parallel Processor Arrays Symbolic System Synthesis Using Answer Set Programming System Integration of Tightly-Coupled Processor Arrays using Reconfigurable Buffer Structures Szenarienbasierte Integration von Diagnosefunktionalität in E/E Architekturen Timing Analysis of Ethernet AVB-based Automotive E/E Architectures Transactor-based Prototyping of Heterogeneous Multiprocessor System-On-Chip Architectures Virtual Networks - Distributed Communication Resource Management
	2012 A Co-simulation Approach for System-Level Analysis of Embedded Control Systems A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays (to appear) A Model-Based Inter-Process Resource Sharing Approach for High-Level Synthesis of Dataflow Graphs A Prototype of an Invasive Tightly-Coupled Processor Array A Very Fast and Quasi-Accurate Power-State-Based System-Level Power Modeling Methodology Actor-oriented Modeling and Simulation of Cut-through Communication in Network Controllers An Integrated Simulation Framework for Invasive Computing Approximate Time Functional Simulation of Resource-Aware Programming Concepts for Heterogeneous MPSoCs Automatic Optimization of In-Flight Memory Transactions for GPU Accelerators based on a Domain-Specific Language for Medical Imaging Combining Formal Model-Based System-Level Design with SystemC Transaction Level Modeling Concepts and Algorithms to Increase the Efficiency and Reliability of Reconfigurable Computer Considering Diagnosis Functionality during Automatic System-Level Design of Automotive Networks Considering MOST150 during Virtual Prototyping of Automotive E/E Architectures Cross-Level Compositional Reliability Analysis for Embedded Systems Design of Low Power On-Chip Processor Arrays Designing FlexRay-based Automotive Architectures: A Holistic OEM Approach Dynamic Defragmentation of Reconfigurable Devices Dynamic Task-Scheduling and Resource Management for GPU Accelerators in Medical Imaging Eine Aktor-Orientierte Methodik zur Power-Modellierung auf Systemebene Ethernet and IP for Automotive E/E-Architectures - Technology, Analysis, Migration Concepts and Infrastructure Exploiting Dynamic Hardware Reconfigurability for Efficiency, Performance, and Reliability Exploiting Model-Knowledge in High-Level Synthesis Fairness in Academic Timetabling Fast Architecture Evaluation of Heterogeneous MPSoCs by Host-Compiled Simulation FlexRay Static Segment Scheduling FPGA-based Testbed for Timing Behavior Evaluation of the Controller Area Network (CAN) Generating Device-specific GPU Code for Local Operators in Medical Imaging Hardware-assisted Decentralized Resource Management for Networks on Chip with QoS Hardware/Software Co-Design: Past, Present, and Predicting the Future Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays Improving Performance of Controller Area Network (CAN) by Adaptive Message Scheduling Invasive Computing - Concepts and Overheads Invasive Manycore Architectures Mastering Software Variant Explosion for GPU Accelerators Model-Based Virtual Prototype Acceleration Neue Möglichkeiten mit Cyber-Physical Systems On-the-fly Composition of FPGA-Based SQL Query Accelerators Using A Partially Reconfigurable Module Library Partial Reconfiguration on FPGAs in Practice - Tools and Applications Placing Multi-mode Streaming Applications on Dynamically Partially Reconfigurable Architectures Power Management Strategies for Serial RapidIO Endpoints in FPGAs Simulation of Resource-Aware Applications on Heterogeneous Architectures Symbolic loop parallelization of static control programs Symbolic System-level Design Methodology for Multi-Mode Reconfigurable Systems System Level Synthesis Flow for Self-adaptive Multi-mode Reconfigurable Systems System-Level Modeling and Simulation of Networked PROFINET IO Controllers Systematic Design of Self-Adaptive Embedded Systems with Applications in Image Processing The Spectral Relation between the Cube-Connected Cycles and the Shuffle-Exchange Network Towards Domain-specific Computing for Stencil Codes in HPC Unreliable Data Transmissions and Limited Hardware Communication Buffers in Automotive E/E Virtual Prototypes Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis Virtual Prototyping for Efficient Multi-Core ECU Development of Driver Assistance Systems
	2011 A Co-Simulation Approach for Control Performance Analysis during Design Space Exploration of Cyber-Physical Systems A Flexible Smart Camera System based on a Partially Reconfigurable Dynamic FPGA-SoC A Rule-Based Static Dataflow Clustering Algorithm for Efficient Embedded Software Synthesis Accuracy of Ethernet AVB Time Synchronization Under Varying Temperature Conditions for Automotive Networks Actor-oriented Modeling of Industrial Ethernet in the Automation Domain Using SystemC An Automated Data Structure Migration Concept - From CAN to Ethernet/IP in Automotive Embedded Systems (CANoverIP) An FPGA Implementation of a Threat-based Strategy for Connect6 Analyzing Automotive Networks using Virtual Prototypes Automatic Generation of System-Level Virtual Prototypes from Streaming Application Models Automatic System-Level Synthesis: From Formal Application Models to Generic Bus-Based MPSoCs Bitonic Sorting on Dynamically Reconfigurable Architectures Calibration and Validation of Software Performance Models for Pedestrian Detection Systems Control Performance-Aware System Level Design Decentralized Dynamic Resource Management Support for Massively Parallel Processor Arrays Dependability-Aware System-Level Design for Embedded Systems Design and Architectures for Dependable Embedded Systems Design of Image Processing Embedded Systems Using Multidimensional Data Flow Detector Defect Correction of Medical Images on Graphics Processors Discrete Particle Swarm Optimization for TSP: Theoretical Results and Experimental Evaluations Distributed Resource Reservation in Massively Parallel Processor Arrays Distributed Self-organizing Bandwidth Allocation for Priority-based Bus Communication Dynamic Decentralized Mapping of Tree-Structured Applications on NoC Architectures DynOAA - Dynamic Offset Adaptation Algorithm for Improving Response Times of CAN Systems Efficient Evaluation of Power/Area/Latency Design Trade-offs for Coarse-Grained Reconfigurable Processor Arrays Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards ESL Power and Performance Estimation for Heterogeneous MPSoCs Using SystemC Exploring the Benefits of Randomized Instruction Scheduling Frameworks for GPU Accelerators: A Comprehensive Evaluation using 2D/3D Image Registration Frameworks for Multi-core Architectures: A Comprehensive Evaluation using 2D/3D Image Registration Gateway Strategies for Embedding of Automotive CAN-frames into Ethernet-packets and Vice Versa Generating GPU Code from a High-level Representation for Image Processing Kernels Heterogeneous Constraint Handling for Particle Swarm Optimization Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays Invasive Computing: An Overview Mapping of Applications to MPSoCs Operational Mode Exploration for Reconfigurable Systems with Multiple Applications Opt4J - A Modular Framework for Meta-heuristic Optimization OrganicBus: Organic Self-organising Bus-Based Communication Systems Parallel Sorting - The Need for Speed Proceedings of the 22nd IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP) Resource-Aware Programming and Simulation of MPSoC Architectures through Extension of X10 RITK: The Range Imaging Toolkit - A Framework for 3-D Range Image Stream Processing Runtime Stress-Aware Replica Placement on Reconfigurable Devices under Safety Constraints Scalable Many-Domain Power Gating in Coarse-grained Reconfigurable Processor Arrays Self-organized Message Scheduling for Asynchronous Distributed Embedded Systems Situation Aware Scheduling for Enery-Efficient Real-Time-Systems Stress-Aware Module Placement on Reconfigurable Devices Symbolic Design Space Exploration for Multi-Mode Reconfigurable Systems Symbolic System Synthesis in the Presence of Stringent Real-Time Constraints Testing Switched Ethernet Networks in Automotive Embedded Systems Towards Resource-Aware Programming on Intel's Single-Chip Cloud Computer Processor Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays Unifying Partitioning and Placement for SAT-based Exploration of Heterogeneous Reconfigurable SoCs Velocity Adaptation in Particle Swarm Optimization Verifying the Authorship of Embedded IP Cores: Watermarking and Core Identification Techniques (Keynote)
	2010 3-SAT on CUDA: Towards a Massively Parallel SAT Solver A Bus-based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs A Deeply Pipelined and Parallel Architecture for Denoising Medical Images A Novel Event Insertion Heuristic for Finding Feasible Solutions of Course Timetabling Problems A Rapid Prototyping System for Error-Resilient Multi-Processor Systems-on-Chip A System-Level Synthesis Approach from Formal Application Models to Generic Bus-Based MPSoCs Actor-oriented Modeling of Driver Assistance Systems for Efficient Multi-Core ECU Implementation Adaptive Traffic Scheduling Techniques for Mixed Real-Time and Streaming Applications on Reconfigurable Hardware Analysis of SystemC actor networks for efficient synthesis Communication Synthesis of Loop Accelerator Pipelines Comparison of Parallelization Frameworks for Shared Memory Multi-Core Architectures Compilation Techniques for CGRAs: Exploring All Parallelization Approaches Design and Experimental Evaluation of Multiple Adaptation Layers in Self-optimizing Particle Swarm Optimization Digitale Hardware/Software-Systeme: Spezifikation und Verifikation Discourse on Extending Embedded Medical Image Processing Systems Using the High Speed Serial RapidIO Interconnect Dynamically Reconfigurable Systems - Architectures, Design Methods and Applications Echtzeitanalyse Ethernet-basierter E/E-Architekturen im Automobil Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs Efficient High-Level Modeling in the Networking Domain Electromagnetic Compatibility (EMC) of CAN+ Erlangen Slot Machine: An FPGA-Based Dynamically Reconfigurable Computing Platform Improving Bitonic Sorting by Wire Elimination Improving Platform-Based System Synthesis by Satisfiability Modulo Theories Solving Integrated Modeling Using Finite State Machines and Dataflow Graphs Integrating Hardware/Firmware Verification Efforts Using SystemC High-Level Models Interprocedural Placement-Aware Configuration Prefetching for FPGA-based Systems Invasive Computing - Basic Concepts and Foreseen Benefits Lifetime Reliability Optimization for Embedded Systems: A System-Level Approach Modeling and Synthesis of Communication Subsystems for Loop Accelerator Pipelines Multiplexing Methods for Power Watermarking Network Bandwidth Optimization of Ethernet-based Streaming Applications in Automotive Embedded Systems New Directions for FPGA IP Core Watermarking and Identification Placing Streaming Applications with Similarities on Dynamically Partially Reconfigurable Architectures Proc. 21st IEEE International Conference on Application-specific Systems, Architectures, and Processors ReCoNets – Design Methodology for Embedded Systems Consisting of Small Networks of Reconfigurable Nodes and Connections ReCoNodes - Optimization Methods for Module Scheduling and Placement on Reconfigurable Hardware Devices Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays Robust Design of Embedded Systems Robustness Analysis of Watermark Verification Techniques for FPGA Netlist Cores SEIS - Sicherheit in Eingebetteten IP-Basierten Systemen Self-Organizing Computer Vision for Robust Object Tracking in Smart Cameras Self-organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-based Bus Communication Symbolic System Level Reliability Analysis Techniques for Increasing Security and Reliability of IP Cores Embedded in FPGA and ASIC Designs Towards Scalable System-Level Reliability Analysis Using the Power Side Channel of FPGAs for Communication Virtual Area Management: Multitasking on Dynamically Partially Reconfigurable Devices
	2009 A Communication Architecture for Complex Runtime Reconfigurable Systems and its Implementation on Spartan-3 FPGAs A Holistic Approach for Tightly Coupled Reconfigurable Parallel Processors Acceleration of a Relative Positioning Framework Acceleration of Multiresolution Imaging Algorithms: A Comparative Study AIS-Autonomous Integrated Systems CAN+: A New Backward-compatible Controller Area Network (CAN) Protocol with up to 16x Higher Data Rates CAN+: Techniques and Prototype for Achieving Increased Data Rates on the Basis of Common CAN Bus Structures Combined System Synthesis and Communication Architecture Exploration for MPSoCs Concepts for run-time and error-resilient control flow checking of embedded RISC CPUs Data Flow Based System Level Design and Analysis of Concurrent Image Processing Applications Designing Heterogeneous ECU Networks via Compact Architecture Encoding and Hybrid Timing Analysis Designing Multi-Processor Systems-on-Chip Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs Efficient Mapping of Multiresolution Image Filtering Algorithms on Graphics Processors Electronic System-Level Synthesis Methodologies ESL Synthesis Across Hardware/Software Boundaries Exploiting Data-Redundancy in Reliability-Aware Networked Embedded System Design FlexRay Schedule Optimization of the Static Segment FPGA Implementation of an Invasive Computing Architecture From Dynamic Reconfiguration to Self-Configuration: Invasive Algorithms and Architectures From Model-based Design to Virtual Prototypes for Automotive Applications FSM-Controlled Architectures for Linear Invasion General Methodology for Mapping Iterative Aproximation Algorithms to Adaptive Dynamically Partially Reconfigurable Systems Impact of Loop Tiling on the Controller Logic of Hardware Acceleration Engines Incorporating Graceful Degradation into Embedded System Design Minimizing Internal Fragmentation by Fine-grained Two-dimensional Module Placement for Runtime Reconfigurable Systems Model-Based Synthesis and Optimization of Static Multi-Rate Image Processing Algorithms Model-based Virtual Prototyping for Automotive Applications Modeling and Simulation of IEEE 802.11g using OMNeT++ Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators Optimization Flow for Algorithm Mapping on Graphics Cards Parallelization Approaches for Hardware Accelerators - Loop Unrolling versus Loop Partitioning PARO – A Design Tool for the Automatic Generation of Hardware Accelerators Particle Swarm Optimization with Velocity Adaptation Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC using Modular Performance Analysis Power-efficient Reconfiguration Control in Coarse-grained Dynamically Reconfigurable Architectures Practice: ESL Case Studies (Motion-JPEG Example) Principles: Analysis, Optimization and Exploration Run time Mapping of AdaptiveApplications onto Homogeneous NoC-based Reconfigurable Architectures Scheduling Techniques for High-Throughput Loop Accelerators Self-Organizing Bandwidth Sharing in Priority-based Medium Access Self-Organizing Multi-cue Fusion for FPGA-based Embedded Imaging Symbolic Scheduling of SystemC Dataflow Designs System Integration of Tightly-Coupled Reconfigurable Processor Arrays and Evaluation of Buffer Size Effects on Their Performance System Level Performance Simulation for Heterogeneous Multi-Processor Architectures SYSTEMCODESIGNER - An Automatic ESL Synthesis Approach by Design Space Exploration and Behavioral Synthesis for Streaming Applications SystemCoDesigner: An ESL Synthesis Methodology Testfallgenerierung für SystemC-Designs mit abstrakten Modellbeschreibungen The Future of ESL Synthesis
	2008 3D Person Tracking with a Color-Based Particle Filter A comparison of embedded reconfigurable video-processing architectures A Feasibility-Preserving Crossover and Mutation Operator for Constrained Combinatorial Problems A Feasibility-Preserving Local Search Operator for Constrained Discrete Optimization Problems A Generalized Static Data Flow Clustering Algorithm for MPSoC Scheduling of Multimedia Applications A Sequential Learning Resource Allocation Network for Image Processing Applications An Actor-Oriented Design Methodology Using SystemC Area and Reconfiguration Time Minimization of the Communication Network in Regular 2D Reconfigurable Architectures Automatic Synthesis of Design Alternatives for Fast Stream-Based Out-of-Order Communication Classification of General Data Flow Actors into Known Models of Computation Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures Comparison of One-Dimensional Adaptive Channel Estimation Techniques for OFDM Systems Concepts for Autonomous Control Flow Checking for Embedded CPUs Concepts for Self-Adaptive and Self-Healing Networked Embedded Systems Concurrent Topology and Routing Optimization in Automotive Network Integration Domain-Specific Reconfigurable MPSoC-Systems - Challenges and Trends Dynamic Reconfiguration of FlexRay Schedules for Response Time Reduction in Asynchronous Fault-Tolerant Networks Efficient Reconfigurable On-Chip Buses for FPGAs Efficient Symbolic Multi-Objective Design Space Exploration Entdecke die Möglichkeiten ESL Methodologies for Platform-Based Synthesis Heuristics for Scheduling Reconfigurable Devices with Consideration of Reconfiguration Overheads Invasion - A New Parallel Computing and Architecture Paradigm Invasive Algorithms and Architectures MAML: An ADL for Designing Single and Multiprocessor Architectures Multi-Objective Routing and Topology Optimization in Networked Embedded Systems Netlist-Level IP Protection by Watermarking for LUT-Based FPGAs No-Break Dynamic Defragmentation of Reconfigurable Devices Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures Paralleles Sortieren - Parallel geht schnell PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications Power Signature Watermarking of IP Cores for FPGAs Power-efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures Quantitative Evaluation of Behavioral Synthesis Approaches for Reconfigurable Devices ReCoBus-Builder - A Novel Tool and Technique to Build Statically and Dynamically Reconfigurable Systems for FPGAs Reconfigurability Issues of Future Massively Parallel SoCs Reconfigurable HW/SW Architecture of a Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System Semi-Automatic Generation of mixed Hardware-Software Prototypes from Simulink Models Social Interaction in Particle Swarm Optimization, the Ranked FIPS, and Adaptive Multi-Swarms Symbolic Quasi-Static Scheduling of Actor-Oriented SystemC Models Symbolic Reliability Analysis and Optimization of ECU Networks Symbolic Reliability Analysis of Self-healing Networked Embedded Systems Symbolic Voter Placement for Dependability-Aware System Synthesis Symbolische Modellprüfung Aktor-orientierter High-level SystemC-Modelle mit Intervalldiagrammen Synthesis of Multi-Dimensional High-Speed FIFOs for Out-of-Order Communication SystemCoDesigner - A Methodology for an Early Assessment of Design Options SystemCoDesigner - An ESL Design Methodology Based on the FunState MoC SystemCoDesigner - Map2MPSoC 2008 SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models SystemCoDesigner: Automatic Design Space Exploration and Rapid Prototyping from Behavioral Models The PAULA Language for Designing Multi-Dimensional Dataflow-Intensive Applications Theoretical Analysis of Initial Particle Swarm Behavior Topology-Aware Replica Placement in Fault-Tolerant Embedded Networks Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism
	2007 A SystemC-based Design Methodology for Digital Signal Processing Systems A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation Actor-Oriented Modeling and Simulation of Sliding Window Image Processing Algorithms Autonomic MPSoCs for Reliable Systems Bitstream Decompression for High Speed FPGA Configuration from Slow Memories Communication Aware Optimization of the Task Binding in Hardware/Software Reconfigurable Networks Concepts for Autonomic Integrated Systems Design space exploration of reliable networked embedded systems Digitale Hardware/Software-Systeme: Synthese und Optimierung Dynamically Reconfigurable Architectures Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays Efficient Event-driven Simulation of Parallel Processor Architectures Efficient Hardware Checkpointing -- Concepts, Overhead Analysis, and Implementation Efficient Reconfigurable On-Chip Buses Exploration, Partitioning and Simulation of Reconfigurable Systems Formalizing TLM with Communicating State Machines Mapping Actor-Oriented Models to TLM Architectures Massively Parallel Processor Architectures: A Co-design Approach Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen Modeling and Synthesis of Hardware-Software Morphing Modeling of Interconnection Networks in Massively Parallel Processor Architectures Offline and Online Aspects of Defragmenting the Module Layout of a Partially Reconfigurable Device Particle Swarm Optimization in High-Dimensional Bounded Search Spaces Periodic Load Balancing on the N-Cycle: Analytical and Experimental Evaluation Reconfigurable Computing Systems Registration of measured and simulated non-ideal geometry using optimization methods Reliability-Aware System Synthesis SAT-Decoding in Evolutionary Algorithms for Discrete Constrained Optimization Problems Scheduling and communication-aware mapping of HW-SW modules for dynamically and partially reconfigurable SoC architectures Schwach-programmiert macht stark Simulative Buffer Analysis of Local Image Processing Algorithms Described by Windowed Synchronous Data Flow Solving Multiobjective Pseudo-Boolean Problems Symbolic Archive Representation for a Fast Nondominance Test Synthese zuverlässiger und flexibler Systeme System Level Modeling and Performance Simulation for Dynamic Reconfigurable Computing Systems in SystemC The Erlangen Slot Machine: A Platform for Interdisciplinary Research in Reconfigurable Computing Time Synchronization Towards a Unified Execution Model for Transactions in TLM Watermarking Apparatus, Software Enabling an Implementation of an Electronic Circuit Comprising a Watermark, Method for Detecting a Watermark and Apparatus for Detecting a Watermark
	2006 06141 Abstracts Collection -- Dynamically Reconfigurable Architectures A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template A Flexible Reconfiguration Manager for the Erlangen Slot Machine A Formal Methodology for Hierarchical Partitioning of Piecewise Linear Algorithms A Generic Framework for Rapid Prototyping of System-on-Chip Designs A Highly Parameterizable Parallel Processor Array Architecture An Architecture Description Language for Massively Parallel Processor Architectures An FPGA-Based Dynamically Reconfigurable Platform: from Concept to Realization An Operating System Infrastructure for Fault-Tolerant Reconfigurable Networks Analysis of Dataflow Programs with Interval-limited Data-rates Approximationsalgorithmen - Eine Einführung Are Current ESL Tools Meeting the Requirements of Advanced Embedded Systems? Assertion-Based Verification of Transaction Level Models Automatic Test Case Generation with Model Checker NuSMV Automatic Test Generation with Model Checking Techniques Bridging the Gap between Relocation and Available Technology: The Erlangen Slot Machine Communication-conscious Mapping of Regular Nested Loop Programs onto Massively Parallel Processor Arrays Concepts for Self-Adaptive Automotive Control Architectures Controller Synthesis for Mapping Partitioned Programs on Array Architectures Designing Low Power Hardware / Software Systems Dynamic Task Binding for Hardware/Software Reconfigurable Networks Efficient Representation and Simulation of Model-Based Designs in SystemC Eine modellbasierte Entwurfsmethodik für SystemC Formalizing TLM with Communicating State Machines FPGA Core Watermarking Based on Power Signature Analysis Hardware Cost Analysis for Weakly Programmable Processor Arrays Hierarchical Partitioning for Piecewise Linear Algorithms Higher-dimensional packing with order constraints (to appear) Identifying FPGA IP-Cores based on Lookup Table Content Analysis Improving Automatic Design Space Exploration by Integrating Symbolic Techniques into Multi-Objective Evolutionary Algorithms Improving System Level Design Space Exploration by Incorporating SAT-Solvers into Multi-Objective Evolutionary Algorithms MAML - An Architecture Description Language for Modeling and Simulation of Processor Array Architectures, Part I Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays: Architectural Parameters and Methodology Mapping of Nested Loop Programs onto Massively Parallel Processor Arrays with Memory and I/O Constraints Minimizing communication cost for reconfigurable slot modules Model-Based Embedded System Design Modeling and Analysis of Windowed Synchronous Algorithms Modeling and Design of Fault-Tolerant and Self-Adaptive Reconfigurable Networked Embedded Systems Modeling of Interconnection Networks in Massively Parallel Processor Architectures Multi-Objective Topology Optimization for Networked Embedded Systems Online Placement for Dynamically Reconfigurable Devices Placing Functionality in Fault-Tolerant Hardware/Software Reconfigurable Networks Power Aware Design Searching RC5-Keys with Distributed Reconfigurable Computing Stochastic Timing Analysis of Communicating Tasks with Internal State SystemCoDesigner - Eine Entwurfsmethodik für SystemC-Beschreibungen SystemCoDesigner - Eine Entwurfsmethodik für SystemC-Beschreibungen SysteMoC - Verification and Refinement of Actor-Based Models of Computation Task-Accurate Performance Modeling in SystemC for Real-Time Multi-Processor Architectures The Erlangen Slot Machine: A Dynamically Reconfigurable FPGA-Based Computer The Renaissance of FPGA-Based High-Performance Computing Timing Analysis of Systems of Communicating Tasks with Internal State Topic 18: Embedded Parallel Systems Von der Hollerith-Maschine zum Parallelrechner
	2005 A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices A System-Level Approach to Hardware Reconfigurable Systems Abstract-Sammlung des 51ten Workshops über Datenstrukturen, Effiziente Algorithmen und Komplexitätstheorie Automatic FIR Filter Generation for FPGAs Automatic Model-Based Design Space Exploration for Embedded Systems - A System Level Approach Automatische Verification von ADeVA-Spezifikationen Co-Design of Massively Parallel Embedded Processor Architectures Cognitronics Comparison of Techniques for the Automatic Verification of ADeVA Specifications Control Path Generation for Mapping Partitioned Dataflow-dominant Algorithms onto Array Architectures Defragmenting the Module Layout of a Partially Reconfigurable Device Design Space Exploration for Systems on FPGA Design Space Exploration of Actor Based Specifications on FPGA Distributed HW/SW-Partitioning for Embedded Reconfigurable Systems DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices Evaluation of Watermarking methods for FPGA-based IP-cores Improving EA-based Design Space Exploration by Utilizing Symbolic Feasibility Tests Increasing the Flexibility in FPGA-Based Reconfigurable Platforms: The Erlangen Slot Machine Initial Population Construction for Convergence Improvement of MOEAs Kurzperiodisches paralleles Sortieren Leistungsbewertung von InfiniBand HCA-Modellen Model-Based System-Level Design Using SystemC Modeling and Analysis of Indirect Communication in Particle Swarm Optimization Modular Video Streaming on a Reconfigurable Platform Online Hardware/Software Partitioning in Networked Embedded Systems Output Serialization for FPGA-based and Coarse-grained Processor Arrays Packet Routing in Dynamically Changing Networks on Chip Paralleles Sortieren - Klassiker, Überrraschungen, Motor Partial Configuration Design and Implementation Challenges on Xilinx Virtex FPGAs Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism Representing Models of Computation in SystemC SPI-Workbench - Modellierung, Analyse und Optimierung eingebetteter Systeme The Erlangen Slot Machine: A Highly Flexible FPGA-Based Reconfigurable Platform The Future of Reconfigurable Computing The Spectra of Popular Hypercubic Networks Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems Verteilte HW/SW-Partitionierung für fehlertolerante rekonfigurierbare Netzwerke Windowed Synchronous Data Flow
	2004 A Dynamic NoC Approach for Communication in Reconfigurable Devices A Dynamic Scheduling and Placement Algorithm for Reconfigurable Hardware A New Approach for On-line Placement on Reconfigurable Devices Analysis of Dataflow Programs with Interval-Limited Data-Rates Architektur und Compiler Co-Design Automatic and Optimized Generation of Compiled High-Speed RTL Simulators Basic OS Support for Distributed Reconfigurable Hardware CAD Software Präsentation Challenges and Potentials of Reconfigurable Computing Challenges and Potentials of Reconfigurable Computing CoreMap: A Rapid Prototyping Environment for Distributed Reconfigurable Systems Covering Pareto-optimal Fronts by Subswarms in Multi-objective Particle Swarm Optimization Design and Implementation of Reconfigurable Multiple Bus on Chip (RMBoC) Design Automation for Massively Parallel Processor Arrays: Transforming Regular Algorithms to Reconfigurable Hardware Design Space Exploration for Distributed Hardware Reconfigurable Systems Designing Partial and Dynamically Reconfigurable Applications on Xilinx Virtex-II FPGAs using HandelC Distributed Arithmetic for Recursive Convolution of Optical Interconnects Dynamic Piecewise Linear/Regular Algorithms Dynamic Reconfiguration of Distributed Arithmetic Controllers: Design Space Exploration and Trade-off Analysis DyNoC-Konzepte für Temporale On-Chip-Netzwerke DyNoC-Konzepte für Temporale On-Chip-Netzwerke Efficient Architecture/Compiler Co-Exploration for ASIPs and ASAPs Energy Estimation and Optimization for Piecewise Regular Processor Arrays Entwurfsraumexploration rekonfigurierbarer Netze FPGA Architecture Extensions for Preemptive Multitasking and Hardware Defragmentation Generation of Distributed Arithmetic Designs for Reconfigurable Applications Hardware-Software-Partitioning with SystemC High-Speed Event-Driven RTL Compiled Simulation Implementierung komplexer Algorithmen in FPGAs Introduction to Hardware-Software-Co-Design Mapping a Class of Dependence Algorithms to Coarse-grained Reconfigurable Arrays -- Architectural Parameters and Methodology Mapping of Computational Intensive Programms to Massively Parallel Architectures Mapping of Regular Algorithms to Massively Parallel Architectures Mapping of Regular Nested Loop Programs to Coarse-grained Reconfigurable Arrays -- Constraints and Methodology Modeling and Analysis of Distributed Reconfigurable Hardware Molecular Force Field Parameterization using Multi-Objective Evolutionary Algorithms Multi-objective Evolutionary Algorithms. Data Structures, Convergence, and Diversity Multi-Objective Particle Swarm Optimization Multikriterieller Entwurf mechatronischer Systeme On-line Placement and Routing in Reconfigurable Devices On-line Placement for Dynamic Reconfigurable Devices Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices Optimization Algorithms for Dynamic Reconfigurable Embedded Systems Particle Swarms for Multi-Objective Optimization Platform-Independent Methodology for Partial Reconfiguration Preemptive Hardware Task Management Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism ReCoNets: Hardware-rekonfigurierbare Netze Regular Mapping for Coarse-grained Reconfigurable Architectures Rekonfigurierbare Kommunikationsstrukturen auf dem Chip-Projekt ReCoNodes Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals Resource Constrained and Speculative Scheduling of Dynamic Piecewise Regular Algorithms Systematic Integration of Parameterized Local Search Into Evolutionary Algorithms Systematic Integration of Parameterized Local Search Techniques in Evolutionary Algorithms Task Scheduling for Heterogeneous Reconfigurable Computers The Erlanger Slot Machine (ESM) The Randomized Sample Tree: A Data Structure for Externally Stored Virtual Environments
	2003 A Fully Self-Timed Bit-Serial Pipeline Architecture for Embedded Systems A High Performance VLIW Processor for Finite Field Arithmetic A Model for Buffer Exploration in EDF Scheduled Embedded Systems A New Approach for Reconfigurable Massively Parallel Computers A New Approach of a Self-Timed Bit-Serial Synchronous Pipeline Architecture Accelerating Design Space Exploration Accelerating Design Space Exploration Using Pareto-Front Arithmetics Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms Basic OS Support for Distributed Reconfigurable Hardware Buildabong: A Framework for Architecture/Compiler Co-Exploration Covering Pareto Sets by Multilevel Evolutionary Subdivision Techniques Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware Domain-Specific Processors: Systems, Architectures, Modeling and Simulation Efficient Implementation of the Singular Value Decomposition on a Reconfigurable System Entwurfsautomatisierung elektronischer Systeme auf Systemebene Fault Tolerance Analysis of Distributed Reconfigurable Systems Using SAT-Based Techniques FPGA Designs of Parallel High Performance GF(2^233^) Multipliers Hierachical Synthesis of Embedded Systems Using Evolutionary Algorithms Improved time domain simulation of optical multimode intrasystem interconnects Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System Quad-trees: A Data structure for storing Pareto-sets in Multi-objective Evolutionary Algorithms with Elitism ReCoNets: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware Run-time Exchange of Mechatronic Controllers Using Partial Hardware Reconfiguration SAT-Based Techniques in System Synthesis Solving Hierarchical Optimization Problems Using MOEAs Speeding up Online Placement for XILINX FPGAs by Reducing Configuration Overhead Strategies for finding good local guides Synthesis of Dataflow Graphs for Reconfigurable Systems using Temporal Partitioning and Temporal Placement Synthesizing Passive Networks by applying Genetic Programming and Evolution Strategies Temporal Task Clustering for Online Placement on Reconfigurable Hardware The role of e-dominance in Multi-Objective Particle Swarm Optimization Methods
	2002 (Self-) reconfigurable Finite State Machines ??? Architecture/Compiler Co-Exploration for ASIPs Comparison of Data Structures for Storing Pareto-sets in MOEAs Efficient Architecture/Compiler Co-Exploration for ASIPs Energy Estimation for Piecewise Regular Processor Arrays Energy Estimation of Nested Loop Programs Exact Partitioning of Affine Dependence Algorithms Flexibility / Cost-Tradeoffs of Platform-Based Systems Generation of Distributed Loop Control Interface Synthesis for FPGA Based VLSI Processor Arrays Modellierung Rekonfigurierbarer Systemarchitekturen Reconfigurable Implementation of Elliptic Curve Crypto Algorithms SPI - A System Model for Heterogeneously Specified Embedded Systems SPI-Workbench für die Analyse eingebetteter Systeme System Design for Flexibility Tradeoff Analysis of FPGA Based Elliptic Curve Cryptography Transformation of SDL Specifications for System-Level Timing Analysis
	2001 Boundary Control: A new Distributed Control Architecture for Space-Time Tranformed (VLSI) Processor Arrays Design Space Characterization for Architecture/Compiler Co-Exploration Design Space Exploration for Massively Parallel Processor Arrays Exact Partitioning of Affine Dependence Algorithms Extending Partial Suborders FunState - An Internal Design Representation for Codesign Hardware Supported Sorting: Design and Tradeoff Analysis Hierarchical Microprocessor Design Using XASM Hierarchical Modeling and Simulation of Embedded Processors Using ASMs Higher-Dimensional Packing with Order Constraints Hybrid Global/Local Search Strategies for Dynamic Voltage Scaling in Embedded Multiprocessors Optimal FPGA Module Placement with Temporal Precedence Constraints Optimization of Dynamic Hardware Reconfigurations Pareto-Front Exploration with Uncertain Objectives Symbiose von Hardware und Software Synthesis and Optimization of Digital Hardware/Software Systems Synthesis of FPGA Implementations from Loop Algorithms
	2000 A Joined Architecture/Compiler Environment for ASIPs Automated Design Space Exploration on System Level for Embedded Systems BUILDABONG: A Rapid Prototyping Environment for ASIPs Description and Simulation of Microprocessor Instruction Sets Using ASMs Description and Simulation of Microprocessor Instruction Sets Using ASMs Embedded System Design using the SPI Workbench Embedded System Synthesis and Optimization (Invited paper) Evolutionary Algorithms for the Synthesis of Embedded Software EXPLORA - Generic Design Space Exploration During Embedded System Synthesis Hardware-Supported Sorting: Design and Tradeoff Analysis Multidimensional Exploration of Software Implementations for DSP Algorithms Optimizing the Efficiency of Parameterized Local Search within Global Search P-based System Design with the PARADISE Design Environment Regular State Machines SPI Workbench - Entwurf gemischt reaktiv/transformativer Systeme Symbiose von Hardware und Software Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
	1999 3D Exploration of Software Schedules for DSP Algorithms 3D Exploration of Uniprocessor Schedules for DSP ALgorithms Compile-Time Optimization of Dynamic Hardware Reconfigurations Evolutionary Algorithm Based Exploration of Software Schedules for Digital Signal Processors FunState - An Internal Design Representation for Codesign Hardware/Software Codesign of Embedded Systems - The SPI Workbench Optimized Software Synthesis for DSP Using Randomization Techniques Representation of Function Variants for Embedded System Optimization and Synthesis Scheduling Hardware/Software Systems Using Symbolic Techniques SPI - An Internal Representation for Heterogeneously Specified Embedded Systems
	1998 3D Exploration of Uniprocessor Schedules for DSP Algorithms Buffer Memory Optimization in DSP Applications - An Evolutionary Approach CodeSign: An Embedded System Design Environment Combining Multiple Models of Computation for Scheduling and Allocation Domain-Specific Interface Generation From Dataflow Specifications Interfacing Hardware and Software Optimized Software Synthesis for Digital Processing Algorithms - An Evolutionary Approach Optimized Software Synthesis for Digital Signal Processing Algorithms: An Evolutionary Approach Optimizing Dynamic Hardware Reconfigurations Rapid Prototyping of Dataflow Programs on Hardware/Software Architectures Regular State Machines Representation of Process Mode Correlation for Scheduling SCF - State Machine Controlled Flow Diagrams System-Level Synthesis Using Evolutionary Algorithms
	1997 ??? An Evolutionary Approach to System-Level Synthesis Hardware/Software-Codesign: Massgeschneiderte elektronische Systeme. Teil II: HW/SW-Synthese Partitioning Processor Arrays under Resource Constraints Performance Analysis of Mixed Asynchronous-Synchronous Systems
	1996 A new approach to solving resource-constrained scheduling problems based on a flow-model An evolutionary approach to system-level synthesis Hardware/Software-Codesign: Massgeschneiderte elektronische Systeme.Teil I: HW/SW-Architekturen und Spezifikation Scheduling of partitioned regular algorithms on processor arrays with constrained resources Synthesis and Optimization of Digital Hardware/Software Systems System-level synthesis using evolutionary algorithms
	1995 On finding a minimal enclosing parallelogram Simulation and modeling of heterogeneous systems modeled by deterministic discrete event systems
	1994 Automateddesign of two-dimensional rational decimation systems Families of Smith Form Decompositions to simplify Multidimensional Filter Design On finding a minimal enclosing parallelogram On finding a minimal enclosing parallelogram Performance analysis and optimization of mixed asynchronous synchronous systems Performance Analysis of Mixed Asynchronous-Synchronous Systems
	1993 A Compiler for Application-Specific Processor Arrays A Compiler for Application-Specific Processor Arrays (Zugl. Doktorarbeit) Minimal communication in massively parallel architectures Partitioning of processor arrays: A piecewise regular approach
	1992 A transformative approach to the partitioning of processor arrays Control generation in the design of processor array Hierarchical concepts in the design of processor arrays The concepts of COMPAR: A compiler for massive parallel architectures
	1991 Control generation in the design of processor arrays Uniform design of parallel programs for DSP
	1990 Design of configurable processor arrays (invited paper) Systematic design concepts for signal processing arrays (invited paper)



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