Hardware-Software-Co-Design
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Design and Implementation of Signal Processing Software [DISPS]
KO; Blockveranstaltung 15.12.2005-22.12.2005 Mo-Fr, Sa, So, 14:00 - 15:30, 205
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WPF CE-MA 5
WPF EEI-DH 5
WPF INF-DH-HSCD 5
WPF IuK-DH 5
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Bhattacharyya, S.
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Exercise for Design and Implementation of Signal Processing Software [UE-DISPS]
UE; Blockveranstaltung 15.12.2005-22.12.2005 Mo-Fr, Sa, So, 15:30 - 17:00, 205
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Bhattacharyya, S.
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VORL; 2 SWS; ECTS: 4; auch für Computational Engineering; Di, 8:30 - 10:00, K1, (außer Di 15.11.2005); 8:30 - 10:00, Raum n.V.; Einzeltermin am 15.11.2005, 8:30 - 10:00, 2.038
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WPF CE-BA-INF 5
WPF INF-DH-HSCD 5
WPF IuK-DH-ES-INF1 5-6
WPF IuK-DH-REA-INF1 5-6
WPF IuK-DH-VSPS-INF2 5-6
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Hannig, F.
Streichert, Th.
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UE; 2 SWS; ECTS: 4; auch für Computational Engineering
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WPF CE-BA-INF 5
WPF INF-DH-HSCD 5
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| | | Di | 16:00 - 18:00 | 2.038 | |
Streichert, Th. | | |
| | | Mi | 16:00 - 18:00 | 00.151 | |
Dutta, H. | | |
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VORL; 2 SWS; ECTS: 4; auch für Computational Engineering und I&K; Do, 14:00 - 16:00, H4
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WPF INF-DH-HSCD 5-7
PF IuK-DG 3
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Wanka, R.
Haubelt, Ch.
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UE; 2 SWS; ECTS: 4; auch für Computational Engineering und I&K
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WPF INF-DH-HSCD 5-7
WPF IuK-DG 3
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| | | Di | 8:00 - 10:00 | 00.151 | |
Helwig, S. | | |
| | | Di | 8:30 - 10:00 | E 1.12 | |
Schlichter, Th. | | |
| | | Fr | 14:00 - 16:00 | 2.038 | |
Schlichter, Th.
Helwig, S. | | |
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Reconfigurable Computing [RC]
VORL; 2 SWS; ECTS: 4; Informatik/Elektrotechnik/Mathematik/Computational Engineering; Mi, 14:00 - 16:00, 00.151
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WPF INF-DH-HSCD 5-7
WPF IuK-DH-ES-INF2 5-7
WPF IuK-DH-REA-INF1 5-7
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Teich, J.
Majer, M.
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Exercises to Reconfigurable Computing [UE-RC]
UE; Mo, 16:00 - 18:00, 00.152
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WPF INF-DH-HSCD 5-7
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Majer, M.
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Praktikum zu Reconfigurable Computing [PR-RC]
PR; Mo, 16:30 - 18:00, 204
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Majer, M.
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