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Reconfigurable Computing (RC-VU)5 ECTS (englische Bezeichnung: Reconfigurable Computing)
(Prüfungsordnungsmodul: Reconfigurable Computing (Lecture with Exercises))
Modulverantwortliche/r: Jürgen Teich Lehrende:
Jürgen Teich
Startsemester: |
WS 2022/2023 | Dauer: |
1 Semester | Turnus: |
jährlich (WS) |
Präsenzzeit: |
60 Std. | Eigenstudium: |
90 Std. | Sprache: |
Englisch |
Lehrveranstaltungen:
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Reconfigurable Computing
(Vorlesung, 2 SWS, Jürgen Teich, Do, 08:15 - 09:45, 01.255-128)
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Exercises to Reconfigurable Computing
(Übung, 2 SWS, Tobias Hahn et al., Mo, 16:15 - 17:45, 02.134-113)
Inhalt:
Content: Reconfigurable (adaptive) computing is a novel yet important research field investigating the capability of hardware to adapt to changing computational requirements such as emerging standards, late design changes, and even to changing processing requirements arising at run-time. Reconfigurable computing thus benefits from a) the programmability of software similar to the Von Neumann computer and b) the speed and efficiency of parallel hardware execution.
The purpose of the course reconfigurable computing is to instruct students about the possibilities and rapidly growing interest in adaptive hardware and corresponding design techniques by providing them the necessary knowledge for understanding and designing reconfigurable hardware systems and studying applications benefiting from dynamic hardware reconfiguration.
After a general introduction about benefits and application ranges of reconfigurable (adaptive) computing in contrast to general-purpose and application-specific computing, the following topics will be covered:
Reconfigurable computing systems: Introduction of available technology including fine grained look up table (LUT-) based reconfigurable systems such as field programmable gate arrays (FPGA) as well as newest coarse grained architectures and technology.
Design and implementation: Algorithms and steps (design entry, functional simulation, logic synthesis, technology mapping, place and route, bit stream generation) to implement (map) algorithms to FPGAs. The main focus lies on logic synthesis algorithms for FPGAs, in particular LUT technology mapping.
Temporal partitioning: techniques to reconfigure systems over time. Covered are the problems of mapping large circuits which do not fit one single device. Several temporal partitioning techniques are studied and compared.
Temporal placement: Techniques and algorithms to exploit the possibility of partial and dynamic (run-time) hardware reconfiguration. Here, OS-like services are needed that optimize the allocation and scheduling of modules at run-time.
On-line communication: Modules dynamically placed at run-time on a given device need to communicate as well as transport data off-chip. State-of-the-art techniques are introduced how modules can communicate data at run-time including bus-oriented as well as network-on-a-chip (NoC) approaches.
Designing reconfigurable applications on Xilinx Virtex FPGAs: In this part, the generation of partial bitstreams for components to be placed at run-time on Xilinx FPGAs is introduced and discussed including newest available tool flows.
Applications: This section presents applications benefiting from dynamic hardware reconfiguration. It covers the use of reconfigurable systems including rapid prototyping, reconfigurable supercomputers, reconfigurable massively parallel computers and studies important application domains such as distributed arithmetic, signal processing, network packet processing, control design, and cryptography.
Lernziele und Kompetenzen:
Learning objectives and competencies:
- Wissen
- The students know to exploit run-time reconfigurable design methodologies for adaptive applications.
- Verstehen
- The students understand the mapping steps, and optimization algorithms.
The students classify different types and kinds of reconfigurable hardware technologies available today.
The students clarify pros and cons of reconfigurable computing technology.
The students summarize applications benefiting from reconfigurable computing.
The students describe the design of circuits and systems-on-a-chip (SoC) on FPGAs.
Literatur:
Bemerkung:
Reconfigurable computing is an interdisciplinary field of research between computer science and electrical engineering.
Organisatorisches:
Selection of this module prohibits the selection of the module "Reconfigurable Computing with Extended Exercises (RC-VEU)" by the student.
Weitere Informationen:
www: https://www.cs12.tf.fau.de/lehre/lehrveranstaltungen/vorlesungen/reconfigurable-computing/
Verwendbarkeit des Moduls / Einpassung in den Musterstudienplan:
- Medizintechnik (Master of Science)
(Po-Vers. 2019w | TechFak | Medizintechnik (Master of Science) | Modulgruppen M1, M2, M3, M5, M7 nach Studienrichtungen | Study Field Health and Medical Data Analytics | M2 Engineering Core Modules (HMDA) | Reconfigurable Computing (Lecture with Exercises))
Dieses Modul ist daneben auch in den Studienfächern "Advanced Signal Processing & Communications Engineering (Master of Science)", "Informatik (Bachelor of Arts (2 Fächer))", "Informatik (Bachelor of Science)", "Informatik (Master of Science)", "Informations- und Kommunikationstechnik (Master of Science)", "Mathematik (Bachelor of Science)", "Mechatronik (Bachelor of Science)", "Mechatronik (Master of Science)" verwendbar. Details
Studien-/Prüfungsleistungen:
Reconfigurable Computing (Lecture with Exercises) (Prüfungsnummer: 741941)
(englischer Titel: Reconfigurable Computing (Lecture with Exercises))
- Prüfungsleistung, mündliche Prüfung, Dauer (in Minuten): 30, benotet, 5 ECTS
- Anteil an der Berechnung der Modulnote: 100.0 %
- weitere Erläuterungen:
Oral examination (Duration: 30 min). The oral examination determines the final grade of the module.
- Prüfungssprache: Deutsch oder Englisch
- Erstablegung: WS 2022/2023
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