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Praktikum für systematischen Entwurf programmierbarer Logikbausteine (PR PLD)
- Lecturer
- M. Sc. Torsten Reißland, Akad. Rat
- Details
- Praktikum
3 cred.h, certificate, compulsory attendance, ECTS studies, ECTS credits: 2,5, Sprache Deutsch, 1-wöchiges Blockpraktikum
Time and place: 9:00 - 17:00, EL 4.13; comments on time and place: 1-wöchiges Blockpraktikum
- Fields of study
- WPF WING-BA-IKS-ING-P 4-6
WPF WING-MA 1-4
WPF WING-BA-ET-IT 3-6
WPF EEI-BA-AET 5-6
WPF EEI-BA-INT 5-6
WPF EEI-BA-MIK 5-6
WPF EEI-MA-AET 1-4
WPF EEI-MA-INT 1-4
WPF EEI-MA-MIK 1-4
WPF ME-MA-P 1-4
WPF WING-MA-ET-IT 1-3
- Prerequisites / Organisational information
- Vorkenntnisse: Grundlagen digitaler Schaltungen
- Contents
- Schaltungen: 7-Segment-Decoder, Multiplexer, Zähler
Eingabe: Fuse-map, VHDL, Zustandsdiagramm, Schaltplan, Bibliothek
Bausteine: PLDs, FPGAs
Versuchsinhalte: Schaltnetze, Multiplex-Anzeige, Stoppuhr
In System Programming (isp)
- Recommended literature
- Tietze/Schenk: Halbleiter-Schaltungstechnik, Springer Verlag
- ECTS information:
- Title:
- Practical Course for Systematic Design with Programmable Logic Devices (PLD)
- Credits: 2,5
- Prerequisites
- Basics in digital circuits and logic
- Contents
- Circuits: 7 segment display, multiplexer, counter
Input: fuse map, VHDL, state diagram, schematic, library
Devices: PLDs, FPGAs
Chapters: combinatorial circuits, sequential circuits, multiplexing display, stop watch
In system programming (ISP)
- Literature
- Tietze/Schenk: Halbleiter-Schaltungstechnik, Springer Verlag
- Additional information
- Keywords: Digitale Schaltungen, Schaltnetze, Schaltwerke, PLD, FPGA, VHDL, Altera, Simulation
Expected participants: 20, Maximale Teilnehmerzahl: 20
www: https://www.studon.fau.de/cat1826887.html Registration is required for this lecture. Die Registration via: StudOn
- Verwendung in folgenden UnivIS-Modulen
- Startsemester WS 2020/2021:
- Praktikum für systematischen Entwurf programmierbarer Logikbausteine (PR PLD)
- Department: Chair of Electronics (Prof. Dr. Weigel)
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