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Departments
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Faculty of Engineering
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Department of Computer Science
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Chair of Computer Science 3 (Hardware Architectures)
2022
Application Runtime Estimation for AURIX Embedded MCU Using Deep Learning
Investigating SAMV Regarding its Suitability For FPGAs
2021
A Versatile, Voltage-Pulse Based Read and Programming Circuit for Multi-Level RRAM Cells
Brain-inspired Computing: E = AI 2
Fast HBM Access with FPGAs: Analysis, Architectures, and Applications
RISC-V3: A RISC-V Compatible CPU with a Data Path Based on Redundant Number Systems
Simulating large neural networks embedding MLC RRAM as weight storage considering device variations
Taming Non-Deterministic Low-Level I/O: Predictable Multi-Core Real-Time Systems by SoC Co-Design
The HERA Methodology: Reconfigurable Logic in General-Purpose Computing
Transparent FPGA Acceleration with TensorFlow
2020
A Model-to-Circuit Compiler for Evaluation of DNN Accelerators based on Systolic Arrays and Multibit Emerging Memories
Embedded Computer Systems: Architectures, Modeling, and Simulation
Impact of Performance Estimation on Fast Processor Simulators
2019
A First-Principles Approach to Performance, Power, and Energy Models for Contemporary Multi- and Many-Core Processors
A Generic Functional Simulation of Heterogeneous Systems
A Hardware Inference Accelerator for Temporal Convolutional Networks
Evaluating HSA-Compatible Heterogeneous Systems for ADAS Applications
Optimizing Multi-State Reliability in ReRAM Arrays using an Automated Device Selection Method
Simulating Memristive Systems in Mixed-Signal Mode using Commercial Design Tools
Utilizing PYNQ for Accelerating Image Processing Functions in ADAS Applications
2018
A flexible mixed-signal image processing pipeline using 3D chip stacks
A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model
A New Generic HLS Approach for Heterogeneous Computing: On the Feasibility of High-Level Synthesis in HSA-Compatible Systems
A programmable ternary CPU using hybrid CMOS/ memristor circuits
Application-Specific Tailoring of Multi-Core SoCs for Real-Time Systems with Diverse Predictability Demands
Automated Instruction Stream Throughput Prediction for Intel and AMD Microarchitectures
Autonomes Fahren
Autonomous Driving in the Curriculum of Computer Architecture
Comparison of Lane Detection Algorithms for ADAS using Embedded Hardware Architectures
Conceptual design of a RISC-V compatible processor core using ternary arithmetic unit with memristive MLC storage
Embedded Fluorescence Lifetime Determination for High-Throughput, Low-Photon-Number Applications
Evaluation of a Sensor Fusion Algorithm on a Real-Time Processor
Heterogeneous Computing Utilizing FPGAs
High-Endurance Bipolar ReRAM-Based Non-Volatile Flip-Flops with Run-Time Tunable Resistive States
Latency Measurements for an Emulation Platform on Autonomous Driving Platform NVIDIA Drive PX2
Multi-Level Memristive Voltage Divider: Programming Scheme Trade-offs
On the Accuracy and Usefulness of Analytic Energy Models for Contemporary Multicore Processors
Programmable HSA Accelerators for Zynq UltraScale+ MPSoC Systems
SC17 student cluster competition, Team Technical University of Munich and Friedrich-Alexander University Erlangen-Nürnberg: Reproducing vectorization of the Tersoff multi-body potential on the Intel Broadwell architecture
Simulating Memristive Networks in SystemC-AMS
The NAS Benchmark Kernels for Single and Multi-Tenant Cloud Instances with LXC/KVM
2017
A fast general purpose CPU utilizing signed-digit encoding and multi-bit memristors
A Hybrid Simulation Environment to Estimate the Accuracy, Energy Consumption and Processing Time for Image Processing Applications
A Methodology to Estimate the Energy Consumption and Processing Time for Image Processing Algorithms in Advanced Driver Assistance Systems
A Non-Volatile Flip-Flop Using Memristive Voltage Divider
An Analysis of Core- and Chip-Level Architectural Features in Four Generations of Intel Server Processors
An Extended Analysis of Memory Hierarchies for Efficient Implementations of Image Processing Applications
An Image Processing Operator Language for Design and Synthesis of Smart Camera Architectures
Autonomes Fahren - Hilfe mein Auto fährt von alleine
Comprehensive curriculum for reconfigurable heterogeneous computer architecture education
Embedded Fluorescence Lifetime Determination for High Throughput Real-Time Droplet Sorting with Microfluidics
Estimation of Time Behaviour of Selected Autonomous Driving Algorithms using GPGPU-Sim
Evaluating a Simulation based PLC Processor Optimization
Evaluating Ternary Adders using a hybrid Memristor / CMOS approach
Evaluation of a Processor Simulator Exemplified by a Radar Processing Algorithm
Evaluation of ternary computing approaches with NVM technologies
Exploring low-power Embedded Processors for Ocean Simulation
Fast heterogeneous computing architectures for smart antennas
Fe2vCl2: From Bare Metal to High Performance Computing on Virtual Clusters and Cloud Infrastructure
Forschung am Lehrstuhl Informatik 3 (Rechnerarchitektur) an der FAU
Future Directions concerning Disruptive Technologies
Joint Keynote: Perspectives of Memristor and NVM technologies for HPC and embedded computing
Keynote HPX: A high-level approach to standardize asynchronous and massive parallelism in C++
LibHSA: One Step Towards Mastering the Era of Heterogeneous Hardware Accelerators using FPGAs
Memory Analysis and Performance Modeling for HPC Applications on Embedded Hardware via Instruction Accurate Simulation
Memristive Computing
Memristive Devices for Computing: Beyond CMOS and Beyond von Neumann
Memristive Technology for Computing: Opportunities and Challenges
Memristive Voltage Divider: A Bipolar ReRAM-based Unit for Non-Volatile Flip-Flops
One Model to Program Them All: OpenCL for CPU, GPU and FPGA
Processor Error Detection Capabilities of Random Programs
Prototyping memristors in digital system with an FPGA-based testing environment
Reproducibility report: Team SegFAUlt @ SCC 2016
System on Chip Generation for Multi-Sensor and Sensor Fusion Applications
The Best of Both: High-performance and Deterministic Real-Time Executive by Application-Specific Multi-Core SoCs
2016
A SystemC Based Framework for Cycle Accurate Processor Simulation and Parameter Analysis
An Application-Specific Instruction Set Processor for Power Quality Monitoring
An ECM-based Energy-efficiency Optimization Approach for Bandwidth-limited Streaming Kernels on Recent Intel Xeon Processors
Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks
C++ Classes and Templates for OpenCL Kernels with PATOS
Cache Aware Instruction Accurate Simulation of a 3-D Coastal Ocean Model on Low Power Hardware
Cellular Neural Networks for FPGAs with OpenCL
Cellular Neural Networks for FPGAs with OpenCL
Challenges in High Speed Image Processing
Comparison of Common Parallel Architectures for the Execution of the Island Model and the Global Parallelization of Evolutionary Algorithms
Dataflow Optimization for Programmable Embedded Image Preprocessing Accelerators
Embedded Parallel Computing Accelerators for Smart Control Units of Frequency Converters
Evaluating Performance and Energy-efficiency of a Parallel Signal Correlation Algorithm on Current Multi and Manycore Architectures
Evaluating Signed-digit Arithmetic Circuits using Multi-level storing Memristors
Evaluating Signed-digit Arithmetic Circuits using Multi-level storing Memristors
Evaluating Ternary Adders using a Hybrid Memristor/CMOS Approach
Fast and Resource Aware Image Processing Operators Utilizing Highly Configurable IP Blocks
FPGA-aware Transformations of LLVM-IR
Generation of Executable Runtime Constrained Random Programs Functional Processor Verification
Hybrid Code Description for Developing Fast and Resource Efficient Image Processing Architectures
Improving instruction accurate simulation for parallel automotive applications
Investigation of Strategies for an Increasing Population Size in Multi-objective CMA-ES
IPAS: a design framework for analysis, synthesis and optimization of image processing applications for heterogenous computing architectures
Keynote Image Processing Applications for Heterogeneous Computing Architectures
Performance analysis of the Kahan-enhanced scalar product on current multi-corecore and many-core processors
Performance Analysis of the Kahan-Enhanced Scalar Product on Current Multicore Processors
Performance-Engineering-Techniken für moderne Multi- und Manycore-Systeme
Report on Disruptive Technologies for years 2020 - 2030
Short-, mid- and long- term perspectives of memristors for digital computing
Smart Sensor Framework: A Pressure Sensor for Smart Home Applications
Teaching Heterogeneous Computer Architectures Using Smart Camera Systems
The AllScale Runtime Interface: Theoretical Foundation and Concept
The R2-D2 Toolchain – Automated Porting of Safety-Critical Applications to FPGAs
Unkonventionelle Computerarchitekturen: Rechnen mit Lichtquanten, Molekülen und Ionen
Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits
Using Memristor Technology for Multi-value Registers in Signed-digit Arithmetic Circuits
Virtualization Guided Tsunami and Storm Surge Simulations for Low Power Architectures
2015
A Fine-Grained Configurable Cache Architecture for Soft Processors
A Holistic Approach for Modeling and Synthesis of Image Processing Applications for Heterogeneous Computing Architectures
Architecture and Simulation of a Hybrid Memristive Multiplier Network using Redundant Number Representation
Architecture and simulation of a hybrid memristive multiplier network using redundant number representation
Automatic Optimization of Hardware Accelerators for Image Processing
Building the next Generation ADCIRC Code – the HPC Perspective
Digital Read/Write Controller Interface to Multi-bit Memristors used as Registers in Ternary Arithmetic Units
Drei-wertige Logiken mittels Multi-stabiler Speicherelemente
Estimation of Non-functional Properties for Embedded Hardware with Application to Image Processing
Execution-Cache-Memory Performance Model: Introduction and Validation
FAUPU - A Design Framework for the Development of Programmable Image Processing Architectures
Framework for Parameter Analysis of FPGA-based Image Processing Architectures
FREACSIM - A Framework for Creating and Simulating Real-Time Capable Network on Chip Systems and Applications
From Crystals to Hurricanes – How to Scale Simulations Across 7 Orders of Magnitude
Hardware-software co-simulation for medical X-ray control units
IPOL - A Domain Specific Language for Image Processing Applications
Keynote More than the Machine – Using Memristors for Computing
Learn How to Create Petascale Computer Simulations With CUDA and LibGeoDecomp
Multi-GPU Based Evaluation and Analysis of Prehistoric Ice Cores Using OpenCL
Novel Image Processing Architecture for 3D Integrated Circuits
OpenCL 2.0 for FPGAs using OCLAcc
Real-Time Correlation for Locating Systems Utilizing Heterogeneous Computing Architectures
SmartEco: An Integrated Solution from Load Balancing between the Grid and Consumers to Local Energy Efficiency
Synthesis and Optimization of Image Processing Accelerators using Domain Knowledge
Ternary Arithmetic Pipeline Architectures using multi-bit Memristors
Ternary Arithmetic Pipeline Architectures using multi-bit Memristors
Test@Cloud - A Platform for Test Execution in the Cloud
Tsunami and Storm Surge Simulation Using Low Power Architectures - Concept and Evaluation
Using HPX and LibGeoDecomp to build ultra-scalable computer simulations
Vergleich gebräuchlicher Parallelrechensysteme für die Beschleunigung evolutionärer Algorithmen demonstriert für den Entwurf miniaturisierter optischer und elektronischer Bauelemente
Verification of specific processor pipeline stages with UVM
2014
A concept for a ternary signed-digit arithmetic unit with memristor based pipeline registers
A Generic Approach for Analysis of White-Light Interferometry Data via User-Defined Algorithms.
A Portable Petascale Framework for Efficient Particle Methods with Custom Interactions
Cloud Computing - Datenflut durch Wolken
Comparing the Performance of Different x86 SIMD Instruction Sets for a Medical Imaging Application on Modern Multi- and Manycore Chips
Conducting Accelerated Computer Simulations at Scale with LibGeoDecomp
Contribution for the Bi-annual HiPEAC Roadmap Survey HiPEAC Network of Excellence Roadmapping Workshop
Designing and Manufacturing of Real Embedded Multi-Core CPUs: A Holistic Teaching Approach in Computer Architecture
Estimating Video Decoding Energies And Processing Times Utilizing Virtual Hardware
Fast and Generic Hardware Architecture for Stereo Block Matching Applications on Embedded Systems
Hetrogene Rechnerarchitekturen für Embedded Vision
HPX -- The Futurization of Computing
HPX by example
HPX by example
HPX: A Task Based Programming Model in a Global Address Space
LibGeoDecomp and HPX
Maestro: A high performance AES encryption/decryption system
OCLAcc - OpenCL for FPGA-Accelerators
OCLAcc: An Open-source Generator for Configurable Logic Block based Accelerators
On the Way to Big Data Applications in Industrial Computed Tomography
Optical Link Testing and Parameters Tuning with a Test System Fully Integrated into FPGA
Parallel embedded computing – from multi-core to heterogeneous architectures using virtualization and future nanotechnologies
Performance Engineering for a Medical Imaging Application on the Intel Xeon Phi Accelerator
Performance Evaluation of the Intel Many Integrated Core Architecture for 3D Image Reconstruction in Computed Tomography
Performance Investigation and Tuning in the Interoperable Cloud4E Platform
Prozessflexible Steuerung von Industrierobotern
Rechnen in der Wolke
Security Aspects of Cloud Computing - Trusted Cloud in Cloud4E
To INT_MAX... and beyond!: exploring large-count support in MPI
Using the Multi-bit Feature of Memristors for Register Files in Signed-Digit Arithmetic Units
Using the multi-bit feature of memristors for register files in signed-digit arithmetic units
Virtualisation and new programming concepts to save energy in compute-intensive environments Workshop "Energy-efficent high performance computing on heterogeneous architectures"
White Light Interferometry on Embedded Hardware - A First Study
2013
A Predictive Performance Model for Stencil Codes on Multicore CPUs
A Scalable Backend for True MMORPGs -- Bringing Supercomputer Tech Back to Gaming
An auto-tuning approach for optimizing base operators for non-destructive testing applications on heterogeneous multi-core architectures
Continuous Integration and Automation for Devops
Extending Heterogeneous Multi Core Processor Architectures for Embedded Wireless Applications
Fast Evolutionary Algorithms: Comparing High Performance Capabilities of CPUs and GPUs
Fast image processing for optical metrology utilizing heterogeneous computer architectures
i3sched - Ein OpenNebula Scheduler für die Oracle Grid Engine
Modeling and Synthesis of mid- and long-term Future Nanotechnologies for Computer Arithmetic Circuits
Modellzentrierter Test in virtualisierten Testumgebungen
Optical multi-Gbps board-to-board interconnection with integrated FPGA-based diagnostics
Performance Investigations of Genetic Algorithms on Graphics Cards
Porting an Engine Control Application to a Virtual Environment by using an Open Source Real Time Operating System
Porting of the transfer-matrix method for multilayer thin-film computations on graphics processing units
Rekonstruktion der renaissancezeitlichen Festungsanlage am Langenbrücker Tor in Lemgo
Services for numerical simulations and optimisations in grids
Services for Numerical Simulations and Optimizations in Grids
Smart Sensor Architectures for Embedded Biosignal Analysis
Testen in der Cloud - Automatisiertes Testen in virtualisierten Umgebungen
The Impact of H.264/AVC on Compression and Non-Destructive Evaluation of Piston Data in Industrial Computed Tomography
Using HPX and LibGeoDecomp for Scaling HPC Applications on Heterogeneous Supercomputers
2012
A Configurable VHDL Template for Parallelization of 3D Stencil Codes on FPGAs
A Generic VHDL Template for 2D Stencil Code Applications on FPGAs
A Predictive Performance Model for Stencil Codes on Multicore CPUs
A Speed-Up Study for a Parallelized White Light Interferometry Preprocessing Algorithm on a Virtual Embedded Multiprocessor System
Akers’s Wavefront Planner - One of the fastest Stencil-based Path Planners on FPGAs
An Architecture Concept for the Scalable Simulation of Dendritic Growth
An Image Processing Pipeline for fast Spot Detection in Smart Camera Systems
Application of the ParalleX execution model to stencil-based problems
Das DAS–Projekt – Die Digitalisierung der Archäologischen Sammlung am Lippischen Landesmuseum Detmold - Schlüssel zur internationalen Vernetzung
Der modellzentrierte Test geht in die Cloud
Design of a Highly Parallel Board-Level-Interconnection with 320 Gbps Capacity
Emerging Computing Paradigms and Their Theoretical and Parctical Support Tools
Evolutionary Design of Active Free Space Optical Networks Based on Digital Mirror Devices
FUTURE COMPUTING 2012 The Fourth International Conference on Future Computational Technologies and Applications
GPU Implementation of a Multiobjective Search Algorithm
Heterogeneous Computer Architectures: An Image Processing Pipeline for Optical Metrology
HPX - A unifying Parallel Runtime System written in C++
Ingredients for Ultra-Scalable Simulation Codes
Leistungsanalyse Evolutionärer Algorithmen auf GPUs im Vergleich zu Multikern-CPUs
LibGeoDecomp - A Library to Make Computer Simulations Scale/Interactive
LibGeoDecomp Developer Guide
On Parallel Software Verification using Boolean Equation Systems
Optical Link Testing and Parameters Tuning with a Test System Fully Integrated into FPGA
Optimization of a Short-Range Proximity Effect Correction Algorithm in E-Beam Lithography Using GPGPUs
Parallel Embedded Computing Architectures
Realizing real-time centroid detection of multiple objects with marching pixels algorithms on programmable customizing hardware
Scaling a Reverse Time Migration Algorithm on the TSUBAME 2.0 Supercomputer
Systeme an die Macht: Welchen Einfluß haben vernetzte Embedded Systems auf unser Leben?
Tuning Runtime Performance für Multi-/Many-Core Architecture Environments
Using Symbolic Substitution Logic as an Automated Design Procedure for QCA Arithmetic Circuits
Was verändert sich durch Cloud Computing? Risiken, Chancen, Potenziale
Wave guiding properties of ribbed surface waveguides in three frequency domains
2011
A New Virtual Hardware Laboratory for Remote FPGA Experiments on Real Hardware
A normative competence structure model for embedded micro- and nanosystems development
A Smart Camera Processing Pipeline for Image Applications Utilizing Marching Pixels
Analytical Model for the Optimization of Self-Organizing Image Processing Systems Utilizing Cellular Automata
ASIC Architecture to Determine Object Centroids from Gray-Scale Images Using Marching Pixels
Collaborative Administration in the Context of Research Computing Systems
Competence Research: Teaching Embedded Micro-Nano Systems
Efficient Implementation of Selected Parallel Path Planning Algorithms on GPUs
Emergent Computing with Marching Pixels for Real-Time Smart Camera Applications
Evolutionary Optimization of Layouts for High Density Free Space Optical Network Links
Fast Dot Correlation in Optical Metrology on GPGPUs
Generic Emergent Computing in Chip Architectures
GPU Implementation of a Multiobjective Search Algorithm
High Performance Stencil Code Algorithms for GPGPUs
High Performance Stencil Code Algorithms for GPGPUs
LibGeoDecomp - How To Create Teraflop Simulations Within Minutes
Parallel Simulation of Dendritic Growth On Unstructured Grids
Parallel simulation of dendritic growth on unstructured grids
Past, Present and Future of LibGeoDecomp, an Auto-parallelizing Stencil Code Library
Performance comparison of designated preprocessing white light interferometry algorithms on emerging multi- and many-core architectures
Service zum Start von Grid-Jobs in virtuellen Machinen
Simulation and Optimized Design of High Density Optical Crossconnect Systems for Massively Parallel Computing Architectures
The DAS-Project - Contribution for the "Day of Archaeology 2011"
Three-Dimensional Crossbar Interconnection Using Planar-Integrated Free-Space Optics and Digital Mirror-Device
2010
An Optimized FPGA Implementation for a Parallel Path Planning Algorithm Based on Marching Pixels
Comparison of Selected Parallel Path Planning Algorithms on GPGPUs and Multi-Core
Condor
Design of a Programmable Architecture for Cellular Automata Based Image Processing for Smart Camera Chips
Dynamically programmable image processor for compact vision systems
Finite-Differenzen-Methoden
Framework for Distributed Evolutionary Algorithms in Computational Grids
Geometrische Zerlegung
Globus-Webservices
Grid Computing für Computational Science
Implementation of an Error-Robust Bucket-Method Algorithm for Elaboration of White Light Interferometry Data on GPGPUs
Leistungsmaße für das parallele Rechnen
Marching Pixels - Rechnen mit Hardware-Agenten im 2D Pixelraum
Nano-technology aware investigations on fault-masking techniques in the presence of high fault probabilities
Parallelisierungstechniken
Performance-Untersuchungen im Multi-Cluster-Grid
Performantes Testen von fehlertoleranten Hard- und Software-System in der virtuellen Maschine FAUmachine
Rapid Prototyping mit FAUmachine am Beispiel einer VHDL-PCI-Soundkarte
Realizing Real-Time Centroid Detection of Multiple Objects with Marching Pixels Algorithms
Rechnender Raum und seine Bedeutung für Unkonventionelle Architekturen und Rechenmethoden
Revising the Trade-off between the Number of Agents and Agent Intelligence
Seamless High Speed Simulation of VHDL Components in the Context of Comprehensive Computing Systems using the Virtual Machine FAUmachine
Sicherheit im Grid
Softwaresysteme für den Betrieb von Grids
Tool for Automated Generation of MPI Typemaps
Umsetzung eines auf Potentialfeldern basierenden Pfadplanungsalgorithmus für die Jenaer Robot Soccer Engine
Unconventional Computing - Reversible Signed Digit Adders for Future Nanocomputing Devices
VHDL-Simulationen - Beispiel einer High-Throughput-Anwendung im Grid
2009
Deterministic High-Speed Simulation of Complex Systems Including Fault-Injection
Distributed vision with smart pixels
Effiziente Nutzung der Cell BE Architektur für Anwendungen aus der optischen Messtechnik
Evaluating the evolvability of emergent agents with different numbers of states
Model-Driven Design and Organic Computing - Two Different but Possibly Accordable Concepts for the Design of Embedded Systems
On the effectiveness of evolution compared to time-consuming full search of optimal 6-state automata
On the usefulness of detecting soft errors in parallel pipelines for high-speed machine vision based on organic computing
Optical Multiplexing Techniques for Photonic Clos Networks in High Performance Computing Architectures
2008
A 2000 frames/s programmable binary image processor chip for real-time machine vision applications
A new marching pixels algorithm for application-specific vision chips for fast detection of objects' centroids
A Parallel Path Planning Approach Based on Organic Computing Principles
A profitability heuristic that reduces the parameter dependence of dynamic load balancing
Analisi di dati
Emergent algorithms for centroid and orientation detection in high-performance embedded cameras
High speed binary image processor for compact real time vision systems
High-Speed Hardware/Software Cosimulation of Complex Systems including Fault-Injection of Detailed VHDL-Models for PC-Components
LibGeoDecomp: A Grid-enabled Library for Geometric Decomposition Codes
Optimierung der Schnittstelle zwischen Hypervisor und Betriebssystemkern bei virtuellen Maschinen
Pollarder: An architecture concept for self-adapting parallel applications in computational science
Solving the problem of enforced restriction to few states while evolving cellular automata
Some remarks on partition lattices
2007
A bio-inspired architecture approach for a one-billion transistor smart CMOS camera chip
A virtual test environment for mpi development: Quick answers to many small questions
An organic computing architecture for visual microprocessors based on marching pixels
Comparison of envolving uniform, nonuniform cellular automaton, and genetic programming for centroid detection with hardware agents
Evaluating fault-tolerant system designs using FAUmachine
Job Distribution Framework for Large Scale Clusters and Grids
Realising emergent image pre-processing tasks in cellular-automaton-alike massively parallel hardware
Simulation of Dendritic Growth for Materials Science in Multi-Cluster Environments
2006
A combined space-time multiplex architecture for a stacked smart sensor chip
A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems
A toolbox for different organic computing algorithms for marching pixels
Building mini-grid environments with virtual private networks: A pragmatic approach
Harpy - High Throughput Computing
Marching pixels: Using organic computing principles in embedded parallel hardware
Parallelization of simulations for various magnetic system models on small-sized cluster computers with mip
Patternbasierte Verifikation objektorientierter Modelle - Methodik, Semantik und Verfahren
Rock'n'Roll: An Engine for the Board Game "EinStein würfelt nicht"
Sogos - a distributed meta level architecture for the self-organizing grid of services
2005
A new organic computing principle for smart cmos camera chips
A parallel analogue-digital photodiode array processor chip with hard-wired morphologic algorithms
Architektur und Realisierung parallelmorphologischer Algorithmen in einem CMOS-Bildsensor
Build a Heterogeneous Cluster with coLinux and openMosix
Closure Systems and Implications
Dependable Computing EDCC-5
Entwicklung einer multiplexbasierten SIMD-Architektur für intelligente on-Chip CMOS Kamerasysteme
Fast Simulation of Stuck-At and Coupling Memory Faults Using FAUmachine
Harpy - Employing a Process Migration Facility and a User Mode Linux for High Throughput Computing
Harpy: A Virtual Machine Based Approach to High-Throughput Cluster Computing
Marching pixels: A new organic computer paradigm for smart sensor processor arrays
Patterns for Model Verification
Rock'n'Roll - A cross-platform engine for the board game "EinStein würfelt nicht"
Software-Tests mit der FAUmachine
View Graphs for Analysis and Testing of Programs at Different Abstraction Levels
2004
A View-based Control Flow Metric
Advanced virtualization techniques for FAUmachine
Advanced virtualization techniques for FAUmachine
An approach for designing and assessing detectors for dependable component-based systems
Analisi di dati
Constructing the Congruence Lattice of a Finite Algebra
Fast Construction of Concept Lattices
Generierung von Plänen für die funktionale Verifikation automatenbasierter Entwürfe
Generierung von Testvorschlägen aus tabellarischen Spezifikationen
Geschäftsprozessmodellierung mit der "Unified Modeling Language (UML)"
Sichtgraphen: Ein Konzept zur gezielten Untersuchung von Kontrollflussstrukturen
Structural Analysis of Explicit Fault-Tolerant Programs
The "More for Less"-Paradox in Transportation Problems with Infinite-Dimensional Supply and Demand Vectors
The "More for Less"-Paradox in Transportation Problems with Infinite-Dimensional Supply and Demand Vectors
Verification and Test of Critical Systems with Patterns and Scenarios in UML
Verlässlichkeitsbenchmarks: Anforderungen und Struktur
Virtuelle PCs und Netzwerke mit FAUmachine
2003
An Optimized Flow for Designing high-speed, large-scale CMOS ASIC SoCs
Dependability Analysis of Business Process Models
Dependability Benchmarking of Linux based Systems
Endliche Hüllensysteme und ihre Implikationenbasen
Event-Driven Energy Accounting for Dynamic Thermal Management
Extending UML towards a Useful OO-Language for Modeling Dependability Features
Formal Specification of a 40GBit/s Sonet/SDH ASIC with ADeVA
Hardware Fault Injection with UMLinux
Projekt ERIKA - Schlussbericht
Reproducible Dependability Benchmarking Experiments Based on Unambiguosus Benchmark Setup Descriptions
Semantics of a Formal Specification Language for Advanced Design and Verification of ASICs (ADeVA)
Specification, Design and Verification of Systems-on-Chip in a Telecom Application
Strukturelle Analyse explizit fehlertoleranter Programme
System im System
UMLinux als Sandbox
2002
An Object Oriented Notation for Modelling Quantitative Aspects
Behavioural Specification for Advanced Design and Verification of ASICs (ADeVA)
Design und Implementierung eines User-Mode-Linux mit Multiprozessor-Fähigkeit
Enhancing System Validation with Behavioural Types
Implementing a User-Mode Linux with Minimal Changes from Original Kernel
Integration of Formal Specification into the Standard ASIC Design Flow
Modellierung von Geschäftsprozessen in der Unified Modeling Language und ihre Transformation in Petrinetze
Modelling Dependable Systems with Patterns
Parkettierung eines Rechtecks mit zwei Karas
Quantitative Analysis of UML Statechart Models of Dependable Systems
Reproducable Dependability Benchmarking Experiments Based on Unambiguous Benchmark Setup Description
Running a Dependability Benchmark for an Oracle Database System
Simulationsbasierte Bewertung fehlertoleranter Festkommarecheneinheiten
Testing the Fault-Tolerance of Networked Systems
UMLinux - A Tool for Testing a Linux System's Fault Tolerance
UMLinux --- A Versatile SWIFI Tool
Verifikation durch Kontrollflussuntersuchung
2001
Assurance Analysis by Scenario-based UML Modeling
Comparing Fault Models to Assess Windows2000 Robustness
DBench: Dependability Benchmarking
Definition einer Sprache für nicht-funktionale Anforderungen und ihre Anwendung in UML-Modellen
Dependability Analysis in the Early Phases of UML Based System Design
Entwicklung fehlertoleranter Festkommarecheneinheiten
Erstellung von Testplänen für verteilte Systeme durch stochastische Modellierung
Framework for Testing the Fault-Tolerance of Systems Including OS and Network Aspects
Generating Test Plans for Distributed Systems with Stochastic Decision Models
IXNOS - Ein Werkzeug zur Pfadsuche in interagierenden Zustandsautomaten
Konzeption einer Zwischensprache zur Modellierung von Hard- und Software
Konzeption und Implementierung einer Komponente zur Bewertung der semantischen Konsistenz von dynamischen UML-Modellen
Linking Business Process Models with Performance and Dependability
Modeling Requirements for Dependable Systems with UML Statecharts
Performance and Dependability in Business Process Modeling
Portierung des Photuris Key Agreement Dämonen von OpenBSD nach Linux und Erweiterung um Public Key Authentifizierung mit KeyNote
2000
Analyse von Hardwarefehlern in Vermittlungseinheiten digitaler Netze
Can Visual Models of Dependable Systems Be Evaluated?
Can Visual Models of Dependable Systems Be Evaluated?
Definition und Auswertung erweiterter Fehlerbäume für die Zuverlässigkeitsanalyse technischer Systeme
Design und Implementierung einer Komponente zur Transformation von UML-Aktivitätsdiagrammen in stochastische Petrinetze
Design und Implementierung einer Komponente zur Transformation von UML-StateCharts in stochastische Petrinetze
Design und Implementierung eines verteilten Dateisystems für einen teil-abschaltbaren Workstation-Cluster
Design und Implementierung eines verteilten Objektmanagers für einen wartungsfreundlichen Linux Workstation Cluster
Didaktik und Methodik der Theoretischen Informatik, Motivation und computerunterstütztes Lernen
DistLinux-Projekt Idee und Prototyp
Entwurf und Implementierung von Strategien zur Prozessverwaltung in einem verteilten Linux System
Modelling with Extended Fault Trees
Structured Language for Specifications of Quantitative Requirements
UML Extensions for Quantitative Analysis
1999
Analyzing Safety-critical Systems Using Extended Fault Trees
Can Visual Models of Dependable Systems Be Evaluated?
Combining Fault Trees and Petri-Nets to Model Safety-critical Systems
Evaluation of Dependability Critical Systems based on Guarded Statechart Models
High-level Integrated Design Environment for Dependability (HIDE)
Implementierung von Verfahren zur Analyse von Fehlerbäumen mit Multi-State-Komponenten
Parallel Approaches to the Numerical Transient Analysis of Stochastic Reward Nets
Parallele Lösungen für die stochastische Modellierung
Transformation of Guarded State Charts for Quantitative Evaluation of Dependable Embedded Systems
1998
A reward-based result measure concept for GSPNs
Anwendung von Model Checking Techniken auf VHDL-Modelle mit integrierter Fehlerbeschreibung
Assessment of Analysis and Transformation Techniques
Checking Modification Tolerance
Cipher Instruction Search Attack on the Bus-Encryption Security Microcontroller DS5002FP
Didaktisch orientierte Lehrbuchbeurteilung
Didaktisch-orientierte Beurteilung von Lehrbüchern aus der Theoretischen Informatik
Effiziente Erstellung und Auswertung von Rechnermodellen zur detaillierten Zuverlässigkeitsanalyse
Einführung von Reward-Maßen bei der Modellierung mit stochastischen Petri-Netzen
Fehlertoleranzmaßnahmen für Multiprozessoren und ihre Bewertung
Final Report, Part 1: First Phase Project Overview. Esprit Project 27439 - HIDE
Integration erweiterter Fehlerbäume und generalisierter stochastischer Petrinetze
Kompendium motivierender Beispiele in der Theoretischen Informatik
Modeling Fault-Tolerant System Behavior
Parallele transiente Analyse generalisierter stochastischer Petrinetze unter PVM
Performance and dependability evaluation of scalable massively parallel computer systems with conjoint simulation
Polarized Higher-Order Subtyping
Relational Modeling and Analysis of Fault-Tolerant Software for Reactive Systems
Specification for a reconfigurable optoelectronic VLSI processor suitable for digital signal processing
Specification of Analysis and Transformation Techniques
Specification of Modeling Techniques
Specification of the HIDE Environment
The Demonstrator
Verläßlichkeitsbewertung komplexer Systeme
1997
Comparing Different Fault Models Using VERIFY
Dependable Computing for Critical Applications (DCCA-6)
Hardware-Supported Fault Tolerance for Multiprocessors
System Dependability Analysis using VHDL Models with Integrated Fault Descriptions
VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions
VERIFY: Zuverlässigkeitsanalyse unter Verwendung von VHDL-Modellen mit integrierter Fehlerbeschreibung
Verifying fault-tolerant behavior of state machines
Verifying fault-tolerant behavior of state machines
1996
A Scalable Implementation of Fault Tolerance for Massively Parallel Systems
ATOMS - A tool for Automatic Optimization of Gate-Level VHDL Models for Simulation
Multiprocessor Checking Using Watchdog Processors
Parallelrechner und wissenschaftliches Rechnen
Rechnerarchitektur: Grundzüge des Aufbaus und der Organisation von Rechnerhardware
Simulationsbasierte Zuverlässigkeitsanalyse
The Modular Expandable Multiprocessor System MEMSY
VHDL-based Fault Injection with VERIFY
1995
Combining Software-Implemented and Simulation-Based Fault Injection into a Single Fault Injection Method
Software-Based Concurrent Control Flow Checking
1994
A High-speed Watchdog Processor for Multitasking Systems
Architecture and Realization of the Modular Expandable Multiprocessor System MEMSY
Fault Injection Based Validation of Fault-Tolerant Multiprocessors
Hierarchical Checking of Multiprocessors using Watchdog Processors
1993
Fault Injector using UNIX ptrace Interface
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